The escalating demand for high density and performance impose severe requirements on semiconductor fabrication technology, particularly interconnection technology in terms of providing reliable low RxC (resistance x capacitance) interconnect patterns with higher electromigration resistance, wherein sub-micron vias, contacts and trenches have high aspect ratios.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor “chips” comprising five or more levels of metallization are becoming more prevalent as device geometry shrinks to sub-micron levels.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric on a conductive layer comprising at least one conductive pattern, forming an opening through the interlayer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the interlayer dielectric is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the interlayer dielectric and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. As the length of metal interconnects increases and cross-sectional areas and distances between interconnects decrease, the RxC delay caused by the interconnect wiring increases. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more as in sub-micron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As design rules are reduced to about 0.12 micron and below, the rejection rate due to integrated circuit speed delays significantly reduces production throughput and increases manufacturing costs. Moreover, as line widths decrease electrical conductivity and electromigration resistance become increasingly important.
Cu and Cu alloys have received considerable attention as a candidate for replacing Al in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than Al. In addition, Cu has improved electrical properties vis-à-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring.
An approach to forming Cu plugs and wiring comprises the use of damascene structures employing CMP. However, due to Cu diffusion through interdielectric layer materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium (Ti), titanium-tungsten (TiW), tungsten (W), tungsten nitride (WN), Ti—TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
In implementing Cu metallization, particularly in damascene techniques wherein an opening is formed in a dielectric layer, particularly a dielectric layer having a low dielectric constant, e.g., a dielectric constant less than about 3.9, various reliability, electromigration and resistance issues are generated. Reliability issues stem, in part, from the difficulty in forming a continuous seed layer on a barrier layer in an opening, particularly as the feature sizes continue to shrink into the deep sub-micron regime. For example, an opening is formed in dielectric layer 10, with barrier layer 11 lining the opening, as illustrated in FIG. 1. A seed layer 12 for deposition of Cu is then deposited by physical vapor deposition (PVD). As a result of reduced feature sizes and high aspect ratios, it is extremely difficult to deposit a continuous seed layer lining the sidewalls of the opening. Consequently, sidewall discontinuities in seed layer 12 form, as illustrated by reference numeral 13. In addition, it is even difficult to effectively plate the seed layer 12 on the bottom of the opening. Cu cannot be electroplated on a discontinuous seed layer or where no seed layer exists. Consequently, voids are induced leading to high resistance vias and lines or open circuits.
In U.S. Pat. No. 6,197,181 a method is disclosed comprising electroplating a seed layer enhancement film to repair discontinuities in the Cu seed layer resulting from poor step converage of thinner and thinner physical vapor deposition (PVD) due to an aggressive reduction in feature sizes. However, it was found that such seed layer enhancement films exhibit poor properties, such as an undesirable surface roughness, e.g., an average surface roughness (Ra) greater than 25 Å vis-à-vis an Ra of 5 Å to 7 Å for a conventionally deposited PVD Cu film. Such an undesirable surface roughness is schematically illustrated in FIG. 2, reference character 20 denoting the seed layer enhancement film. It was also found that such a seed layer enhancement film 20 not only exhibits an undesirable surface roughness but also undesirably high impurity concentrations of elements such as carbon, oxygen, nitrogen and hydrogen. In addition, such a seed layer enhancement film 20 exhibits an undesirably high film resistivity, e.g., 2.5 to 6 microOhm-cm vis-à-vis a resistivity of less than 2 microOhm-cm for conventional electroplated Cu films. In addition, it was found that such a seed layer enhancement film 20 contains pinhole voids. As a result, the subsequently deposited electroplated Cu film exhibits high resistivity, high surface roughness and voids, leading to significantly increased via/line resistance and lower circuit speed, in addition to generating electromigration and other reliability issues.
Accordingly, there exists a need for methodology enabling the formation of reliable Cu interconnects with reduced resistivity and reduced voids.